Digital System Design (CSC427) — Notes, Syllabus & Past Questions

Advanced digital design and verification using VHDL or Verilog.

Elective Course8 Chapters

EDA tools, IC manufacturing, logic families (TTL/CMOS), noise margins, propagation delay, and power dissipation.

Review of Boolean algebra, Shannon's expansion theorem, minterms, maxterms, and prime implicants.

K-Map multi-level synthesis (AND-OR, OR-AND, NAND-NAND, NOR-NOR) and standard combinational networks.

Quine-McCluskey method, PROMs, PALs, PLAs, Gate Arrays, and full custom design.

Latches vs edge-triggered flip-flops, level enable, clock synchronization, and synchronous/asynchronous signal handling.

ASM charts, synchronous FSM synthesis, timing behavior, and input/output forming logic.

FPGA architectures, PLD configuration, and hardware description with VHDL.

Combinational and sequential test generation, fault modeling (Stuck-At-0 / Stuck-At-1), and Design for Testability (DFT).

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